RISC-V CPU Pipeline 구현 Posted on January 2, 2021 Pipelining 을 구현한 RISC-V CPU입니다. data hazard, control hazard를 해결하였습니다. [Read More] Tags: RISC-V Verilog Computer architecture
Web Ex Web Ex-description Posted on January 2, 2021 HCI hw3 Web EX 어플리케이션 디자인 [Read More] Tags: JS Xd HTML HCI